View SCG4503_8363004.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? 27 - 64 hz jitter bandwidth phase locked output frequency control intrinsically low jitter crystal oscillator lvpecl outputs with disable function dual input references lor & lol combined alarm output force free run function automatic free run operation on loss of both references a & b input duty cycle tolerant 3.3v dc power supply small size: 1 square inch SCG4503 synchronous clock generator pll 2111 comprehensive drive aurora, illinois 60505 phone: 630-851-4722 fax: 630-851-5040 www.conwin.com bulletin sg082 page 1 of 16 revision 00 date 17 june 05 issued by mbatts
data sheet #: sg082 p age 2 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice absolute maximum rating table 1 symbol parameter minimum nominal maximum units notes v cc power supply voltage -0.5 - +4.0 volts 1.0 v i input voltage -0.5 - +5.5 volts 1.0 t s storage temperature -65.0 - +100 c 1.0 general description the SCG4503 is a mixed-signal phase locked loop generating lvpecl outputs from an intrinsically low jitter, voltage controlled, cr ystal oscillato r. the l vpecl outputs may be disabled. the SCG4503 can lock to one of two external references, which is selectable using the sel ab input select pin. the unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different refer ence duty cycles. the SCG4503 includes an alarm output that indicates deviations from normal operation. if a loss- of-reference (lor) or loss-of-lock (lol) is detected the alarm with indicat e the need fo r a reference rearrangement. if both r eferences a and b are absent the module will enter free run operation. the fr status pin will indicate that the module is in free run operation. frequency stability during free run operation is guaranteed to 20 ppm. additionally the free run mode may be entered manually. the package dimensions are 1? x 1.025? x .45? on a 6 layer fr4 board with castellated pins. parts are assembled using high temperature solder to withstand 63/37 alloys, 180c surface mount reflow processes. maximum dimension package outline figure 1 block diagram figure 2 8 khz phase aligner refb refa sel ab analog filter q qn 1 / n alarm low jitter vcxo free run status force free run enable/ tri-state 33 ? 10 k ? 10 k ? 10 k ? 10 k ? 33 ? dpfd
data sheet #: sg082 p age 3 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0 operation of the device at these or any other condition beyond those listed under operating specifications is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2.0 requires exter nal regulation and supply decoupling. (22 uf, 330 pf) 3.0 3db loop response. 4.0 50-ohm load biased to 1.3 volts. 5.0 entry into free run doesn?t meet requirement for initial 2.33 seconds of self-timing. 6.0 the wider bandwidth of this model may result in a break in the gr-253-core, r5-135 switching mask for observation times of < 50ms 7.0 under rapidly changing input conditions. (-11ppm to +11ppm) operating specifications table 2 symbol parameter minimum nominal maximum units notes r in input reference f requency (cmos) - 8 - khz f out output frequency (lvpecl) - 155.52 - mhz v cc power supply voltage 3.135 3.3 3.465 volts 2.0 i cc power supply current - 250 300 ma 5.0 t o temperature range 0 - 70 c f fr free run frequency range -20 - 20 ppm gain phase gain - - 0.2 db@~0.1hz f cap capture/pull-in range -25 - 25 ppm f bw jitter filter bandwidth 27 - 64 hz 3.0 t jtol input jitter to lerance 31.25 - - s 8 khz ref. units (input jitter frequencies 10 hz) t aq typical acquisition time data acquisition from a cold power-up: phase lock within 12ns: <3 sec. phase lock settled: <3 sec. alarm time: <1 sec. acquisition from free run: phase lock within 12ns: <3 sec. phase lock settled: <3 sec. alarm time: 1 sec. frequency lock with a 20ppm reference frequency step: typically 30ms. phase lock during a switch between equal frequency references: typically 0.1s, no alarm should be issued t rf output rise and fall time (20% 80%) 100 225 350 ps 4.0 dc output duty cycle 40 50 60 % mtie sr mtie at synchronization rearrangement gr-253-core.1999 r5-135 5.0,6.0 dynamic offset range (0- 70) - - 20 ns dynamic offset range (25- 70) - - 13 ns unit to unit phase differential - - 100 ns 7.0 output jitter specifications table 3 jitter bw 10 hz - 1 mhz sonet jitter bw 12 khz - 20 mhz frequency (mhz) ps (rms) m ui ps (rms) m ui 155.52 20 typ. 3.110 typ. 1 max. 0.156 max.
data sheet #: sg082 p age 4 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: a active fr free run mode na not active ra locked to reference a rb locked to reference b u unstable (due to conditions sho wn, switch to active reference or free run) x don?t care input and output characteristics table 4 symbol parameter minimum nominal maximum units notes cmos input and output characteristics v ih high level input voltage 2.0 - 5.5 v v il low level input voltage 0.0 - 0.8 v t io i/o to output valid - - 10 ns c l output capacitance - - 10 pf v oh high level output voltage 2.4 - - v v ol low level output voltage - - 0.4 v t ir input reference pulse width 12.5 - - ns pecl output characteristics v oh high level pecl voltage 2.27 2.34 2.52 v v ol low level pecl voltage 1.49 1.51 1.68 v c l output capacitance - - 10 pf t skew differential output skew - 50 - ps input selection / output response table 5 inputs outputs note reset enable sel ab ref a ref b fr fr status alarm q qn 1 0xxxx 1 xxxfr x 1xxxx x x01 0 0xxx1 1 xxxfr 000aa0 00xxra 001aa0 00xxrb 000naa0 01xxu 001naa0 00xxrb 001ana0 01xxu 000ana0 00xxra 00xnana0 11xxfr
data sheet #: sg082 p age 5 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice typical mtie measurement figure 3 typical tdev measurement figure 4 100.0e-12 1. 0e-9 0.01 0.1 1 10 100 observation window (tau) (sec) mtie (sec) 1.0e-12 10.0e-12 100.0e-12 0. 001 0. 01 0. 1 1 10 100 tau (sec) tdev (sec )
data sheet #: sg082 p age 6 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice typical mtie at synchronization rearrangement. reference b equal to inverse of reference a, no modulation. figure 5 1. 0e-9 10. 0e-9 100. 0e-9 1. 0e-6 10. 0e-6 0. 001 0. 01 0.1 1 10 100 1000 observation window (tau) (sec) mtie (sec) requirement mask object iv e mask *note: the wider bandwidth of this model may result in a break in the gr-253-core, r5-135 switching mask for observation times of <50ms. circuit board footprint & keepout recommendations figure 6 0.8400 [21.34 mm] 1.0400 [26.42 mm] 0.8650 [21.97 mm] 0.1000 [2.54 mm] 0.0350 [0.89 mm] 0.0650 [1.65 mm] 0.1000 [2.54 mm] keep out area 1.0700 [27.18 mm]
data sheet #: sg082 p age 7 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice pin description table 6 pin # pin name pin information note 1 enable/tri-state vcxo enable. (enable = 0, disable = 1 = cmos outputs tri-stated) 9.0 2 tck no connection, internal factory programming input. 8.0 3 tdo no connection, internal factory programming input. 8.0 4 ref a cmos reference frequency input. 5 sel ab input reference select pin. (refa = 0, refb = 1) 9.0 6 reset reset. (reset = 1) 9.0 7 ref b cmos reference frequency input. 8v ee ground. 9fr status free run status. (fr = 1) 10 v cc supply voltage relative to ground. 11 n/c no connection. 8.0 12 alarm loss of reference / lock alarm. (alarm = 1) 13 fr force free run. (phase lock = 0, free run = 1) 9.0 14 tdi no connection, internal factory programming input. 8.0 15 tms no connection, internal factory programming input. 8.0 16 qn lvpecl complementary output. 17 v ee ground. 18 q lvpecl output. notes 8.0 do not connect pin 9.0 input pulled to ground ordering information scg{xxxx}-{fff.fff}{m} xxxx equals a specific model (4503) fff.fff equals the oscillator output frequency (155.52) m equals mhz and is added to all part numbers example: to order an SCG4503 with an oscillator output of 155.52 mhz, order part number SCG4503-155.52m
data sheet #: sg082 p age 8 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice lol (internal signal) phase detector (internal signal) external reference (selected input a or b) internal reference (internal signal) lor (internal signal) 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 start-up region 1 1 alarm output (lor + lol) loss of reference condition alarm timing figure 7 alarmtiming legend use for all alarm timing diagrams tab l e 7 start-up region 1 8 khz reference input < 31.25 sec > 31.25 sec 31.25 sec 2 3 4 125 sec wide range minimum pulse width = 62.5 sec during start-up, the lol alarm will pulse during the first few seconds of operation 5
data sheet #: sg082 p age 9 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice lol (internal signal) phase detector (internal signal) external reference (selected input a or b) internal reference (internal signal) lor (internal signal) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 1 5 alarm output (lor + lol) loss of lock condition alarm timing figure 8
data sheet #: sg082 p age 10 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice ref a ref b alarm sel a/b new reference qualification time lol portion of alarm is blanked 0.5 sec switch from a to b when both are good signals figure 9 r ef a r ef b a larm s el a/b ~8ns switch from a to b when reference b is lost figure 10
data sheet #: sg082 p age 11 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice switch from a to b after reference a is lost figure 11 switch from a to b when a is out of range figure 12 156.25 s (8 khz ref units) 126 s (19.44 mhz ref units) ref a ref b alarm sel a/b new reference qualification time alarm blanked ref a ref b alarm sel a/b new reference qualification time out of range in range alarm blanked
data sheet #: sg082 p age 12 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice switch from a to b when b is out of range figure 13 ref a ref b alarm sel a/b g new reference qualification time 0.5 sec. out of range in range alarm blanked switch from a to b when both references have been lost and ref b returns (automatic free run) figure 14 ref a ref b alarm sel a/b new reference qualification time alarm blanked free run status
data sheet #: sg082 p age 13 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice recommended pecl termination figure 15 50 scgxxx lvpecl output q qn vcc gnd 50 ohm transmission line 3.3 vdc 82 50 ohm transmission line lvpecl input d dn vcc gnd vcc - 2 vdc 3.3 vdc scgxxx lvpecl output q qn vcc gnd lvpecl input d dn vcc gnd 50 130 82 3.3 vdc lvpecl input d dn vcc gnd 3.3 vdc 3.3 vdc 50 ohm transmission line 3.3 vdc 50 ohm transmission line 3.3 vdc scgxxx lvpecl output q qn vcc gnd vcc - 2 vdc 100 50 ohm transmission line 130 3.3 vdc 50 ohm transmis sion line 150 150 if pecl outputs do not drive a long line (< 0.5?), a single 150 ? termination resistor to ground may be used for each pin.
data sheet #: sg082 p age 14 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice tape and reel packaging figure 16
data sheet #: sg082 p age 15 of 16 rev: 00 date: 06/17/05 ? copyright 2005 the connor-winfield corp. all rights reserved specifications subject to change without notice solder profile figure 17 temp 0 100 150 200 250 50 12345678 time (minutes) (deg c) recommended reflow profile peak temp: 217 deg c max rise slope: 1.5 deg c/sec time above 150 c: 100 sec model comparison table table 8 max model input duty oscillator output notes ref freq cycle (s ynchronized output) scg4500 2@8 khz 40/60 77.76 mhz,155.52 mhz,125 mhz basic model SCG4503 2@8 khz 40/60 155.52 mhz 27-64 hz jitter bandwidth scg4510 2@1.544 mhz 40/60 155.52 mhz scg4520 2@19.44 mhz 40/60 77.76 mhz,155.52 mhz scg4540 2@10 khz 40/60 163.84 mhz other low jitter line card solutions from connor-winfield scg51 series single input, jitter filtered with free run, 1 cmos and 3 lvpecl outputs up to 622.08 mhz. scg102a/104a single input, frequency selectable, lvpecl clock smoothers from 77.76 to 777.76 mhz. scg2000 series single input, jitter filtered with 20ppm free run, cmos outputs from 8 khz to 125.0 mhz. scg2500 series dual input, jitter filtered with free run, cmos outputs up to 125.0 mhz. scg3000 series single input, jitter filtered with dual lvpecl outputs. scg4000 series single input, jitter filtered with 20ppm free run, lvpecl outputs from 77.76 mhz to 180 mhz. scg4600 series dual input, jitter filtered with free run, 1 cml differential pair output up to 622.08 mhz.
revision revision date note 00 06/17/05 final release

▲Up To Search▲

Price & Availability of SCG4503

	To Download SCG4503 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .